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Add source code of the uROM generator

Pawel Jablonski authored on 24/01/2021 21:45:08
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urom/src/step.h
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+/*
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+ * Author: Pawel Jablonski
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+ * E-mail: pj@xirx.net
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+ * WWW: xirx.net
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+ * GIT: git.xirx.net
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+ *
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+ * License: You can use this code however you like
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+ * but leave information about the original author.
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+ * Code is free for non-commercial and commercial use.
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+ */
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+
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+#ifndef STEP_H
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+#define STEP_H
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+
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+#include <QVector>
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+
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+#include "ucode.h"
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+
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+/**
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+ * This class contains a single step of the instruction.
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+ * It is a raw describe how to set control lines for the step.
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+ */
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+class Step
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+{
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+	public:
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+		static const int CODE_0_BUS_AR_POSITION = 0; //!< Position of bits for the main reading data bus
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+		static const int CODE_0_BUS_AW_POSITION = 3; //!< Position of bits for the main writing data bus
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+		static const int CODE_0_BUS_B_POSITION = 7; //!< Position of bits for the secondary reading data bus
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+
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+		static const int CODE_1_BUS_C_POSITION = 0; //!< Position of bits for the addressing data bus
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+		static const int CODE_1_FLAG_S_POSITION = 2; //!< Position of bits for the ALU_S flags
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+		static const int CODE_1_FLAG_M_POSITION = 6; //!< Position of bit for the ALU_M flag
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+		static const int CODE_1_FLAG_C_POSITION = 7; //!< Position of bit for the ALU_C flag
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+
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+		static const int CODE_FLAG_S_MASK = 0x0f; //!< Mask for ALU_S flags
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+
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+		//! Line select defines for the main reading data bus
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+		enum class BusAR
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+		{
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+			ABXY = 0, //!< Main and auxiliary registers
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+			D, //!< Hidden data register
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+			IN, //!< Input register
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+			T, //!< ALU temp register
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+			Ram, //!< RAM access
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+			Flash, //!< FLASH access
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+			PCL, //!< Program Counter Low register
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+			PCH, //!< Program Counter High register
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+			Default = 0
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+		};
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+
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+		//! Line select defines for the main writing data bus
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+		enum class BusAW
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+		{
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+			None = 0, //!< Not selected
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+			ABXY, //!< Main and auxiliary registers
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+			D, //!< Hidden data register
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+			OUT, //!< Output register
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+			ALU_T, //!< ALU operation
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+			RPC, //!< Reset Program Counter
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+			I, //!< Instruction register
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+			Ram, //!< RAM access
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+			PCL, //!< Program Counter Low register
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+			PCH, //!< Program Counter High register
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+			MAL, //!< Memory Address Low register
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+			MAH, //!< Memory Address High register
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+			PC_PLUS, //!< Increse Program Counter
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+			SP_PLUS, //!< Increse Stack Pointer
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+			SP_MINUS, //!< Decrese Stack Pointer
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+			RPC_PLUS //!< Reset the step counter and increse Program Counter
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+		};
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+
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+		//! Line select defines for the secondary reading data bus
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+		enum class BusB
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+		{
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+			AB = 0, //!< Main registers
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+			D, //!< Hidden data register
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+			Default = 0
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+		};
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+
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+		//! Line select defines for the addressing data bus
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+		enum class BusC
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+		{
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+			PC = 0, //!< Full 16 bit Program Counter register
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+			MA, //!< Full 16 bit Memory Address register
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+			SP, //!< Full 16 bit Stack Pointer register
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+			XY, //!< Full 16 bit auxiliary register
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+			Default = 0
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+		};
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+
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+		Step(BusAR busAR, BusAW busAW, BusB busB = BusB::Default, BusC busC = BusC::Default, unsigned char aluS = 0, bool aluM = false, bool aluC = false);
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+
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+		const UCode &getUCode() const;
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+
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+	private:
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+		UCode uCode; //!< Parsed microcode for the current step
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+};
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+
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+#endif