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Add source code of the firmware for the IO Board
Pawel Jablonski authored on 05/06/2023 17:01:27
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+;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** |
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+;* File Name : startup_stm32f072xb.s |
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+;* Author : MCD Application Team |
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+;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM toolchain. |
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+;* This module performs: |
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+;* - Set the initial SP |
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+;* - Set the initial PC == Reset_Handler |
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+;* - Set the vector table entries with the exceptions ISR address |
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+;* - Branches to __main in the C library (which eventually |
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+;* calls main()). |
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+;* After Reset the CortexM0 processor is in Thread mode, |
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+;* priority is Privileged, and the Stack is set to Main. |
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+;* <<< Use Configuration Wizard in Context Menu >>> |
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+;******************************************************************************* |
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+;* |
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+;* Redistribution and use in source and binary forms, with or without modification, |
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+;* are permitted provided that the following conditions are met: |
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+;* 1. Redistributions of source code must retain the above copyright notice, |
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+;* this list of conditions and the following disclaimer. |
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+;* 2. Redistributions in binary form must reproduce the above copyright notice, |
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+;* this list of conditions and the following disclaimer in the documentation |
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+;* and/or other materials provided with the distribution. |
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+;* 3. Neither the name of STMicroelectronics nor the names of its contributors |
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+;* may be used to endorse or promote products derived from this software |
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+;* without specific prior written permission. |
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+;* |
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+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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+; |
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+;******************************************************************************* |
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+ |
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+; Amount of memory (in bytes) allocated for Stack |
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+; Tailor this value to your application needs |
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+; <h> Stack Configuration |
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+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> |
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+; </h> |
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+ |
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+Stack_Size EQU 0x00000800 |
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+ |
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+ AREA STACK, NOINIT, READWRITE, ALIGN=3 |
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+Stack_Mem SPACE Stack_Size |
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+__initial_sp |
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+ |
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+ |
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+; <h> Heap Configuration |
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+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> |
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+; </h> |
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+ |
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+Heap_Size EQU 0x00000010 |
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+ |
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+ AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
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+__heap_base |
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+Heap_Mem SPACE Heap_Size |
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+__heap_limit |
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+ |
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+ PRESERVE8 |
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+ THUMB |
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+ |
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+ |
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+; Vector Table Mapped to Address 0 at Reset |
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+ AREA RESET, DATA, READONLY |
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+ EXPORT __Vectors |
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+ EXPORT __Vectors_End |
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+ EXPORT __Vectors_Size |
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+ |
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+__Vectors DCD __initial_sp ; Top of Stack |
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+ DCD Reset_Handler ; Reset Handler |
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+ DCD NMI_Handler ; NMI Handler |
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+ DCD HardFault_Handler ; Hard Fault Handler |
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+ DCD 0 ; Reserved |
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+ DCD 0 ; Reserved |
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+ DCD 0 ; Reserved |
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+ DCD 0 ; Reserved |
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+ DCD 0 ; Reserved |
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+ DCD 0 ; Reserved |
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+ DCD 0 ; Reserved |
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+ DCD SVC_Handler ; SVCall Handler |
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+ DCD 0 ; Reserved |
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+ DCD 0 ; Reserved |
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+ DCD PendSV_Handler ; PendSV Handler |
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+ DCD SysTick_Handler ; SysTick Handler |
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+ |
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+ ; External Interrupts |
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+ DCD WWDG_IRQHandler ; Window Watchdog |
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+ DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect |
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+ DCD RTC_IRQHandler ; RTC through EXTI Line |
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+ DCD FLASH_IRQHandler ; FLASH |
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+ DCD RCC_CRS_IRQHandler ; RCC and CRS |
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+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 |
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+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 |
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+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 |
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+ DCD TSC_IRQHandler ; TS |
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+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 |
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+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 |
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+ DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 |
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+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 |
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+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation |
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+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare |
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+ DCD TIM2_IRQHandler ; TIM2 |
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+ DCD TIM3_IRQHandler ; TIM3 |
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+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC |
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+ DCD TIM7_IRQHandler ; TIM7 |
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+ DCD TIM14_IRQHandler ; TIM14 |
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+ DCD TIM15_IRQHandler ; TIM15 |
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+ DCD TIM16_IRQHandler ; TIM16 |
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+ DCD TIM17_IRQHandler ; TIM17 |
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+ DCD I2C1_IRQHandler ; I2C1 |
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+ DCD I2C2_IRQHandler ; I2C2 |
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+ DCD SPI1_IRQHandler ; SPI1 |
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+ DCD SPI2_IRQHandler ; SPI2 |
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+ DCD USART1_IRQHandler ; USART1 |
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+ DCD USART2_IRQHandler ; USART2 |
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+ DCD USART3_4_IRQHandler ; USART3 & USART4 |
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+ DCD CEC_CAN_IRQHandler ; CEC and CAN |
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+ DCD USB_IRQHandler ; USB |
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+ |
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+__Vectors_End |
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+ |
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+__Vectors_Size EQU __Vectors_End - __Vectors |
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+ |
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+ AREA |.text|, CODE, READONLY |
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+ |
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+; Reset handler routine |
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+Reset_Handler PROC |
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+ EXPORT Reset_Handler [WEAK] |
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+ IMPORT __main |
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+ IMPORT SystemInit |
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+ LDR R0, =SystemInit |
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+ BLX R0 |
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+ LDR R0, =__main |
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+ BX R0 |
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+ ENDP |
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+ |
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+; Dummy Exception Handlers (infinite loops which can be modified) |
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+ |
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+NMI_Handler PROC |
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+ EXPORT NMI_Handler [WEAK] |
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+ B . |
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+ ENDP |
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+HardFault_Handler\ |
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+ PROC |
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+ EXPORT HardFault_Handler [WEAK] |
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+ B . |
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+ ENDP |
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+SVC_Handler PROC |
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+ EXPORT SVC_Handler [WEAK] |
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+ B . |
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+ ENDP |
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+PendSV_Handler PROC |
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+ EXPORT PendSV_Handler [WEAK] |
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+ B . |
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+ ENDP |
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+SysTick_Handler PROC |
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+ EXPORT SysTick_Handler [WEAK] |
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+ B . |
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+ ENDP |
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+ |
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+Default_Handler PROC |
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+ |
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+ EXPORT WWDG_IRQHandler [WEAK] |
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+ EXPORT PVD_VDDIO2_IRQHandler [WEAK] |
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+ EXPORT RTC_IRQHandler [WEAK] |
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+ EXPORT FLASH_IRQHandler [WEAK] |
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+ EXPORT RCC_CRS_IRQHandler [WEAK] |
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+ EXPORT EXTI0_1_IRQHandler [WEAK] |
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+ EXPORT EXTI2_3_IRQHandler [WEAK] |
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+ EXPORT EXTI4_15_IRQHandler [WEAK] |
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+ EXPORT TSC_IRQHandler [WEAK] |
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+ EXPORT DMA1_Channel1_IRQHandler [WEAK] |
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+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
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+ EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] |
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+ EXPORT ADC1_COMP_IRQHandler [WEAK] |
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+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
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+ EXPORT TIM1_CC_IRQHandler [WEAK] |
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+ EXPORT TIM2_IRQHandler [WEAK] |
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+ EXPORT TIM3_IRQHandler [WEAK] |
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+ EXPORT TIM6_DAC_IRQHandler [WEAK] |
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+ EXPORT TIM7_IRQHandler [WEAK] |
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+ EXPORT TIM14_IRQHandler [WEAK] |
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+ EXPORT TIM15_IRQHandler [WEAK] |
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+ EXPORT TIM16_IRQHandler [WEAK] |
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+ EXPORT TIM17_IRQHandler [WEAK] |
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+ EXPORT I2C1_IRQHandler [WEAK] |
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+ EXPORT I2C2_IRQHandler [WEAK] |
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+ EXPORT SPI1_IRQHandler [WEAK] |
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+ EXPORT SPI2_IRQHandler [WEAK] |
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+ EXPORT USART1_IRQHandler [WEAK] |
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+ EXPORT USART2_IRQHandler [WEAK] |
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+ EXPORT USART3_4_IRQHandler [WEAK] |
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+ EXPORT CEC_CAN_IRQHandler [WEAK] |
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+ EXPORT USB_IRQHandler [WEAK] |
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+ |
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+ |
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+WWDG_IRQHandler |
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+PVD_VDDIO2_IRQHandler |
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+RTC_IRQHandler |
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+FLASH_IRQHandler |
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+RCC_CRS_IRQHandler |
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+EXTI0_1_IRQHandler |
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+EXTI2_3_IRQHandler |
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+EXTI4_15_IRQHandler |
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+TSC_IRQHandler |
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+DMA1_Channel1_IRQHandler |
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+DMA1_Channel2_3_IRQHandler |
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+DMA1_Channel4_5_6_7_IRQHandler |
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+ADC1_COMP_IRQHandler |
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+TIM1_BRK_UP_TRG_COM_IRQHandler |
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+TIM1_CC_IRQHandler |
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+TIM2_IRQHandler |
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+TIM3_IRQHandler |
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+TIM6_DAC_IRQHandler |
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+TIM7_IRQHandler |
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+TIM14_IRQHandler |
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+TIM15_IRQHandler |
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+TIM16_IRQHandler |
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+TIM17_IRQHandler |
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+I2C1_IRQHandler |
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+I2C2_IRQHandler |
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+SPI1_IRQHandler |
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+SPI2_IRQHandler |
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+USART1_IRQHandler |
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+USART2_IRQHandler |
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+USART3_4_IRQHandler |
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+CEC_CAN_IRQHandler |
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+USB_IRQHandler |
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+ |
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+ B . |
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+ |
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+ ENDP |
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+ |
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+ ALIGN |
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+ |
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+;******************************************************************************* |
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+; User Stack and Heap initialization |
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+;******************************************************************************* |
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+ IF :DEF:__MICROLIB |
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+ |
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+ EXPORT __initial_sp |
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+ EXPORT __heap_base |
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+ EXPORT __heap_limit |
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+ |
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+ ELSE |
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+ |
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+ IMPORT __use_two_region_memory |
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+ EXPORT __user_initial_stackheap |
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+ |
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+__user_initial_stackheap |
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+ |
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+ LDR R0, = Heap_Mem |
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+ LDR R1, =(Stack_Mem + Stack_Size) |
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+ LDR R2, = (Heap_Mem + Heap_Size) |
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+ LDR R3, = Stack_Mem |
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+ BX LR |
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+ |
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+ ALIGN |
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+ |
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+ ENDIF |
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+ |
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+ END |
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+ |
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+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** |