Browse code
Add source code of the uROM generator
Pawel Jablonski authored on 24/01/2021 21:45:08
Showing 1 changed files
| 1 | 1 |
new file mode 100644 |
| ... | ... |
@@ -0,0 +1,893 @@ |
| 1 |
+/* |
|
| 2 |
+ * Author: Pawel Jablonski |
|
| 3 |
+ * E-mail: pj@xirx.net |
|
| 4 |
+ * WWW: xirx.net |
|
| 5 |
+ * GIT: git.xirx.net |
|
| 6 |
+ * |
|
| 7 |
+ * License: You can use this code however you like |
|
| 8 |
+ * but leave information about the original author. |
|
| 9 |
+ * Code is free for non-commercial and commercial use. |
|
| 10 |
+ */ |
|
| 11 |
+ |
|
| 12 |
+#include "urom.h" |
|
| 13 |
+ |
|
| 14 |
+//! Default constructor for creating an uROM. Generating a full instrution set. |
|
| 15 |
+URom::URom() |
|
| 16 |
+{
|
|
| 17 |
+ Instruction instruction; |
|
| 18 |
+ |
|
| 19 |
+ // LOAD_I + RPC+1 // ====================================================== |
|
| 20 |
+ |
|
| 21 |
+ // NOP |
|
| 22 |
+ // Fill whole instruction table as default |
|
| 23 |
+ for(unsigned int i = 0; i < URomData::INSTRUCTION_QUANTITY; i++) |
|
| 24 |
+ {
|
|
| 25 |
+ instruction = Instruction(static_cast<unsigned char>(i)); |
|
| 26 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 27 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 28 |
+ this->uRomData.addInstruction(instruction); |
|
| 29 |
+ } |
|
| 30 |
+ |
|
| 31 |
+ // LOAD_I + RPC // ======================================================== |
|
| 32 |
+ |
|
| 33 |
+ // HALT |
|
| 34 |
+ instruction = Instruction(0b11111111); |
|
| 35 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 36 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 37 |
+ this->uRomData.addInstruction(instruction); |
|
| 38 |
+ |
|
| 39 |
+ // LOAD_I + STORE + RPC+1 // ============================================== |
|
| 40 |
+ |
|
| 41 |
+ // LDF reg |
|
| 42 |
+ instruction = Instruction(0b00000100, Instruction::Arg::ABXY); |
|
| 43 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 44 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::ABXY, Step::BusB::Default, Step::BusC::XY)); |
|
| 45 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 46 |
+ this->uRomData.addInstruction(instruction); |
|
| 47 |
+ |
|
| 48 |
+ // LDR reg |
|
| 49 |
+ instruction = Instruction(0b00001000, Instruction::Arg::ABXY); |
|
| 50 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 51 |
+ instruction.addStep(Step(Step::BusAR::Ram, Step::BusAW::ABXY, Step::BusB::Default, Step::BusC::XY)); |
|
| 52 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 53 |
+ this->uRomData.addInstruction(instruction); |
|
| 54 |
+ |
|
| 55 |
+ // STR reg |
|
| 56 |
+ instruction = Instruction(0b00001100, Instruction::Arg::ABXY); |
|
| 57 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 58 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::Ram, Step::BusB::Default, Step::BusC::XY)); |
|
| 59 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 60 |
+ this->uRomData.addInstruction(instruction); |
|
| 61 |
+ |
|
| 62 |
+ // MOV reg, reg |
|
| 63 |
+ instruction = Instruction(0b10000000, Instruction::Arg::ABXY, Instruction::Arg::ABXY); |
|
| 64 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 65 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ABXY)); |
|
| 66 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 67 |
+ this->uRomData.addInstruction(instruction); |
|
| 68 |
+ |
|
| 69 |
+ // IN reg |
|
| 70 |
+ instruction = Instruction(0b00010000, Instruction::Arg::ABXY); |
|
| 71 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 72 |
+ instruction.addStep(Step(Step::BusAR::IN, Step::BusAW::ABXY)); |
|
| 73 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 74 |
+ this->uRomData.addInstruction(instruction); |
|
| 75 |
+ |
|
| 76 |
+ // OUT reg |
|
| 77 |
+ instruction = Instruction(0b00010100, Instruction::Arg::ABXY); |
|
| 78 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 79 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::OUT)); |
|
| 80 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 81 |
+ this->uRomData.addInstruction(instruction); |
|
| 82 |
+ |
|
| 83 |
+ // LOAD_I + ALU + RPC+1 // ================================================ |
|
| 84 |
+ |
|
| 85 |
+ // CMP reg, reg |
|
| 86 |
+ instruction = Instruction(0b11100000, Instruction::Arg::AB, Instruction::Arg::ABXY); |
|
| 87 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 88 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b0110, false, true)); |
|
| 89 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 90 |
+ this->uRomData.addInstruction(instruction); |
|
| 91 |
+ |
|
| 92 |
+ // LOAD_I + ALU + STORE + RPC+1 // ======================================== |
|
| 93 |
+ |
|
| 94 |
+ // INC reg |
|
| 95 |
+ instruction = Instruction(0b00011000, Instruction::Arg::ABXY); |
|
| 96 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 97 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, false)); |
|
| 98 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 99 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 100 |
+ this->uRomData.addInstruction(instruction); |
|
| 101 |
+ |
|
| 102 |
+ // INCC reg |
|
| 103 |
+ instruction = Instruction(0b01110000, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Disable); |
|
| 104 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 105 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, false)); |
|
| 106 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 107 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 108 |
+ this->uRomData.addInstruction(instruction); |
|
| 109 |
+ |
|
| 110 |
+ instruction = Instruction(0b01110000, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Enable); |
|
| 111 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 112 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, true)); |
|
| 113 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 114 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 115 |
+ this->uRomData.addInstruction(instruction); |
|
| 116 |
+ |
|
| 117 |
+ // DEC reg |
|
| 118 |
+ instruction = Instruction(0b00011100, Instruction::Arg::ABXY); |
|
| 119 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 120 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1111, false, true)); |
|
| 121 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 122 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 123 |
+ this->uRomData.addInstruction(instruction); |
|
| 124 |
+ |
|
| 125 |
+ // DECC reg |
|
| 126 |
+ instruction = Instruction(0b01110100, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Disable); |
|
| 127 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 128 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1111, false, false)); |
|
| 129 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 130 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 131 |
+ this->uRomData.addInstruction(instruction); |
|
| 132 |
+ |
|
| 133 |
+ instruction = Instruction(0b01110100, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Enable); |
|
| 134 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 135 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1111, false, true)); |
|
| 136 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 137 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 138 |
+ this->uRomData.addInstruction(instruction); |
|
| 139 |
+ |
|
| 140 |
+ // NOT reg |
|
| 141 |
+ instruction = Instruction(0b00100000, Instruction::Arg::ABXY); |
|
| 142 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 143 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, true, false)); |
|
| 144 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 145 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 146 |
+ this->uRomData.addInstruction(instruction); |
|
| 147 |
+ |
|
| 148 |
+ // ADD reg, reg |
|
| 149 |
+ instruction = Instruction(0b10010000, Instruction::Arg::AB, Instruction::Arg::ABXY); |
|
| 150 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 151 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b1001, false, true)); |
|
| 152 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 153 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 154 |
+ this->uRomData.addInstruction(instruction); |
|
| 155 |
+ |
|
| 156 |
+ // ADDC reg, reg |
|
| 157 |
+ instruction = Instruction(0b10011000, Instruction::Arg::AB, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Flag::Disable); |
|
| 158 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 159 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b1001, false, false)); |
|
| 160 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 161 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 162 |
+ this->uRomData.addInstruction(instruction); |
|
| 163 |
+ |
|
| 164 |
+ instruction = Instruction(0b10011000, Instruction::Arg::AB, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Flag::Enable); |
|
| 165 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 166 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b1001, false, true)); |
|
| 167 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 168 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 169 |
+ this->uRomData.addInstruction(instruction); |
|
| 170 |
+ |
|
| 171 |
+ // SUB reg, reg |
|
| 172 |
+ instruction = Instruction(0b10100000, Instruction::Arg::AB, Instruction::Arg::ABXY); |
|
| 173 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 174 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b0110, false, false)); |
|
| 175 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 176 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 177 |
+ this->uRomData.addInstruction(instruction); |
|
| 178 |
+ |
|
| 179 |
+ // SUBC reg, reg |
|
| 180 |
+ instruction = Instruction(0b10101000, Instruction::Arg::AB, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Flag::Disable); |
|
| 181 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 182 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b0110, false, false)); |
|
| 183 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 184 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 185 |
+ this->uRomData.addInstruction(instruction); |
|
| 186 |
+ |
|
| 187 |
+ instruction = Instruction(0b10101000, Instruction::Arg::AB, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Flag::Enable); |
|
| 188 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 189 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b0110, false, true)); |
|
| 190 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 191 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 192 |
+ this->uRomData.addInstruction(instruction); |
|
| 193 |
+ |
|
| 194 |
+ // AND reg, reg |
|
| 195 |
+ instruction = Instruction(0b10110000, Instruction::Arg::AB, Instruction::Arg::ABXY); |
|
| 196 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 197 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b1011, true, false)); |
|
| 198 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 199 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 200 |
+ this->uRomData.addInstruction(instruction); |
|
| 201 |
+ |
|
| 202 |
+ // OR reg, reg |
|
| 203 |
+ instruction = Instruction(0b10111000, Instruction::Arg::AB, Instruction::Arg::ABXY); |
|
| 204 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 205 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b1110, true, false)); |
|
| 206 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 207 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 208 |
+ this->uRomData.addInstruction(instruction); |
|
| 209 |
+ |
|
| 210 |
+ // XOR reg, reg |
|
| 211 |
+ instruction = Instruction(0b11000000, Instruction::Arg::AB, Instruction::Arg::ABXY); |
|
| 212 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 213 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b0110, true, false)); |
|
| 214 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 215 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 216 |
+ this->uRomData.addInstruction(instruction); |
|
| 217 |
+ |
|
| 218 |
+ // SHL reg |
|
| 219 |
+ instruction = Instruction(0b01111000, Instruction::Arg::ABXY); |
|
| 220 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 221 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 222 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 223 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 224 |
+ this->uRomData.addInstruction(instruction); |
|
| 225 |
+ |
|
| 226 |
+ // CLR reg |
|
| 227 |
+ instruction = Instruction(0b11001000, Instruction::Arg::ABXY); |
|
| 228 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 229 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0011, false, false)); |
|
| 230 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 231 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 232 |
+ this->uRomData.addInstruction(instruction); |
|
| 233 |
+ |
|
| 234 |
+ // LOAD_I + 8x ALU + STORE + RPC+1 // ===================================== |
|
| 235 |
+ |
|
| 236 |
+ // SHR reg |
|
| 237 |
+ instruction = Instruction(0b01111100, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Disable); |
|
| 238 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 239 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 240 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 241 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 242 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 243 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 244 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 245 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 246 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 247 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 248 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 249 |
+ this->uRomData.addInstruction(instruction); |
|
| 250 |
+ |
|
| 251 |
+ instruction = Instruction(0b01111100, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Enable); |
|
| 252 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 253 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 254 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 255 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 256 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 257 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 258 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 259 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 260 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 261 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 262 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 263 |
+ this->uRomData.addInstruction(instruction); |
|
| 264 |
+ |
|
| 265 |
+ // SWAP reg |
|
| 266 |
+ instruction = Instruction(0b01101100, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Disable); |
|
| 267 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 268 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 269 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, false)); |
|
| 270 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 271 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, false)); |
|
| 272 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 273 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, false)); |
|
| 274 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, false)); |
|
| 275 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, false)); |
|
| 276 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 277 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 278 |
+ this->uRomData.addInstruction(instruction); |
|
| 279 |
+ |
|
| 280 |
+ instruction = Instruction(0b01101100, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Enable); |
|
| 281 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 282 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 283 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, true)); |
|
| 284 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 285 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, true)); |
|
| 286 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 287 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, true)); |
|
| 288 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1100, false, true)); |
|
| 289 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, true)); |
|
| 290 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 291 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 292 |
+ this->uRomData.addInstruction(instruction); |
|
| 293 |
+ |
|
| 294 |
+ // LOAD_I + PC+1 + STORE + RPC+1 // ======================================= |
|
| 295 |
+ |
|
| 296 |
+ // MOV val, reg |
|
| 297 |
+ instruction = Instruction(0b00100100, Instruction::Arg::Val256, Instruction::Arg::ABXY); |
|
| 298 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 299 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 300 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::ABXY)); |
|
| 301 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 302 |
+ this->uRomData.addInstruction(instruction); |
|
| 303 |
+ |
|
| 304 |
+ // OUT val |
|
| 305 |
+ instruction = Instruction(0b00000010, Instruction::Arg::Val256); |
|
| 306 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 307 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 308 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::OUT)); |
|
| 309 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 310 |
+ this->uRomData.addInstruction(instruction); |
|
| 311 |
+ |
|
| 312 |
+ // LOAD_I + PC+1 + LOAD_D + STORE + RPC+1 // =============================== |
|
| 313 |
+ |
|
| 314 |
+ // STR val |
|
| 315 |
+ instruction = Instruction(0b00000001, Instruction::Arg::Val256); |
|
| 316 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 317 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 318 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 319 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::Ram, Step::BusB::Default, Step::BusC::XY)); |
|
| 320 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 321 |
+ this->uRomData.addInstruction(instruction); |
|
| 322 |
+ |
|
| 323 |
+ // LOAD_I + PC+1 + LOAD_D + ALU + RPC+1 // ================================ |
|
| 324 |
+ |
|
| 325 |
+ // CMP val, reg |
|
| 326 |
+ instruction = Instruction(0b00101000, Instruction::Arg::Val256, Instruction::Arg::ABXY); |
|
| 327 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 328 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 329 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 330 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b0110, false, true)); |
|
| 331 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 332 |
+ this->uRomData.addInstruction(instruction); |
|
| 333 |
+ |
|
| 334 |
+ // LOAD_I + PC+1 + LOAD_D + ALU + STORE + RPC+1 // ======================== |
|
| 335 |
+ |
|
| 336 |
+ // ADD val, reg |
|
| 337 |
+ instruction = Instruction(0b00101100, Instruction::Arg::Val256, Instruction::Arg::ABXY); |
|
| 338 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 339 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 340 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 341 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b1001, false, true)); |
|
| 342 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 343 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 344 |
+ this->uRomData.addInstruction(instruction); |
|
| 345 |
+ |
|
| 346 |
+ // ADDC val, reg |
|
| 347 |
+ instruction = Instruction(0b00110000, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Disable); |
|
| 348 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 349 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 350 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 351 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b1001, false, false)); |
|
| 352 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 353 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 354 |
+ this->uRomData.addInstruction(instruction); |
|
| 355 |
+ |
|
| 356 |
+ instruction = Instruction(0b00110000, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Enable); |
|
| 357 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 358 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 359 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 360 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b1001, false, true)); |
|
| 361 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 362 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 363 |
+ this->uRomData.addInstruction(instruction); |
|
| 364 |
+ |
|
| 365 |
+ // SUB val, reg |
|
| 366 |
+ instruction = Instruction(0b00110100, Instruction::Arg::Val256, Instruction::Arg::ABXY); |
|
| 367 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 368 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 369 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 370 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b0110, false, false)); |
|
| 371 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 372 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 373 |
+ this->uRomData.addInstruction(instruction); |
|
| 374 |
+ |
|
| 375 |
+ // SUBC val, reg |
|
| 376 |
+ instruction = Instruction(0b00111000, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Disable); |
|
| 377 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 378 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 379 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 380 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b0110, false, false)); |
|
| 381 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 382 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 383 |
+ this->uRomData.addInstruction(instruction); |
|
| 384 |
+ |
|
| 385 |
+ instruction = Instruction(0b00111000, Instruction::Arg::ABXY, Instruction::Arg::None, Instruction::Arg::None, Instruction::Flag::Enable); |
|
| 386 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 387 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 388 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 389 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b0110, false, true)); |
|
| 390 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 391 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 392 |
+ this->uRomData.addInstruction(instruction); |
|
| 393 |
+ |
|
| 394 |
+ // AND val, reg |
|
| 395 |
+ instruction = Instruction(0b00111100, Instruction::Arg::Val256, Instruction::Arg::ABXY); |
|
| 396 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 397 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 398 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 399 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b1011, true, false)); |
|
| 400 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 401 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 402 |
+ this->uRomData.addInstruction(instruction); |
|
| 403 |
+ |
|
| 404 |
+ // OR val, reg |
|
| 405 |
+ instruction = Instruction(0b01000000, Instruction::Arg::Val256, Instruction::Arg::ABXY); |
|
| 406 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 407 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 408 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 409 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b1110, true, false)); |
|
| 410 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 411 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 412 |
+ this->uRomData.addInstruction(instruction); |
|
| 413 |
+ |
|
| 414 |
+ // XOR val, reg |
|
| 415 |
+ instruction = Instruction(0b01000100, Instruction::Arg::Val256, Instruction::Arg::ABXY); |
|
| 416 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 417 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 418 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 419 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b0110, true, false)); |
|
| 420 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 421 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 422 |
+ this->uRomData.addInstruction(instruction); |
|
| 423 |
+ |
|
| 424 |
+ // LOAD_I + PC+1 + LOAD_MAL + PC+1 + LOAD_MAH + STORE + RPC+1 // ========== |
|
| 425 |
+ |
|
| 426 |
+ // LDF addr, reg |
|
| 427 |
+ instruction = Instruction(0b01011000, Instruction::Arg::Addr, Instruction::Arg::ABXY); |
|
| 428 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 429 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 430 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAL)); |
|
| 431 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 432 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAH)); |
|
| 433 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::ABXY, Step::BusB::Default, Step::BusC::MA)); |
|
| 434 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 435 |
+ this->uRomData.addInstruction(instruction); |
|
| 436 |
+ |
|
| 437 |
+ // LDR addr, reg |
|
| 438 |
+ instruction = Instruction(0b01011100, Instruction::Arg::Addr, Instruction::Arg::ABXY); |
|
| 439 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 440 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 441 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAL)); |
|
| 442 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 443 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAH)); |
|
| 444 |
+ instruction.addStep(Step(Step::BusAR::Ram, Step::BusAW::ABXY, Step::BusB::Default, Step::BusC::MA)); |
|
| 445 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 446 |
+ this->uRomData.addInstruction(instruction); |
|
| 447 |
+ |
|
| 448 |
+ // STR reg, addr |
|
| 449 |
+ instruction = Instruction(0b01100000, Instruction::Arg::ABXY, Instruction::Arg::Addr); |
|
| 450 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 451 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 452 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAL)); |
|
| 453 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 454 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAH)); |
|
| 455 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::Ram, Step::BusB::Default, Step::BusC::MA)); |
|
| 456 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 457 |
+ this->uRomData.addInstruction(instruction); |
|
| 458 |
+ |
|
| 459 |
+ // LOAD_I + PC+1 + LOAD_D + PC+1 + LOAD_MAL + PC+1 + LOAD_MAH + STORE + RPC+1 // |
|
| 460 |
+ |
|
| 461 |
+ // STR val, addr |
|
| 462 |
+ instruction = Instruction(0b00000011, Instruction::Arg::Val256, Instruction::Arg::Addr); |
|
| 463 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 464 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 465 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 466 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 467 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAL)); |
|
| 468 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 469 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAH)); |
|
| 470 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::Ram, Step::BusB::Default, Step::BusC::MA)); |
|
| 471 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 472 |
+ this->uRomData.addInstruction(instruction); |
|
| 473 |
+ |
|
| 474 |
+ // LOAD_I + LOAD + LOAD + RPC+1 + LOAD_I + LOAD + RPC+1 // ================ |
|
| 475 |
+ |
|
| 476 |
+ // XCHG reg, reg |
|
| 477 |
+ instruction = Instruction(0b11010000, Instruction::Arg::ABXY, Instruction::Arg::ABXY); |
|
| 478 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 479 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::D)); |
|
| 480 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ABXY)); |
|
| 481 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 482 |
+ this->uRomData.addInstruction(instruction); |
|
| 483 |
+ |
|
| 484 |
+ instruction = Instruction(0b11001100, Instruction::Arg::ABXY); |
|
| 485 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 486 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::ABXY)); |
|
| 487 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 488 |
+ this->uRomData.addInstruction(instruction); |
|
| 489 |
+ |
|
| 490 |
+ // LOAD_I + PC+1 + LOAD_MAL + PC+1 + LOAD_MAH + 3x STORE + RPC+1 // ======= |
|
| 491 |
+ |
|
| 492 |
+ // XCHG addr, reg |
|
| 493 |
+ instruction = Instruction(0b01001000, Instruction::Arg::Addr, Instruction::Arg::ABXY); |
|
| 494 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 495 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 496 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAL)); |
|
| 497 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 498 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::MAH)); |
|
| 499 |
+ instruction.addStep(Step(Step::BusAR::Ram, Step::BusAW::D, Step::BusB::Default, Step::BusC::MA)); |
|
| 500 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::Ram, Step::BusB::Default, Step::BusC::MA)); |
|
| 501 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::ABXY)); |
|
| 502 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 503 |
+ this->uRomData.addInstruction(instruction); |
|
| 504 |
+ |
|
| 505 |
+ // LOAD_I + PC+1 + LOAD_PCL + PC+1 + LOAD_PCH + STORE + RESET // ============ |
|
| 506 |
+ |
|
| 507 |
+ // JMP addr |
|
| 508 |
+ instruction = Instruction(0b11110000, Instruction::Arg::Addr); |
|
| 509 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 510 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 511 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 512 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 513 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 514 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 515 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 516 |
+ this->uRomData.addInstruction(instruction); |
|
| 517 |
+ |
|
| 518 |
+ // LOAD_I + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + RESET // ============ |
|
| 519 |
+ // + PC+1 + PC+1 + RPC+1 // ======================================== |
|
| 520 |
+ |
|
| 521 |
+ // JE addr |
|
| 522 |
+ for(int c = 0; c < 2; c++) |
|
| 523 |
+ {
|
|
| 524 |
+ for(int z = 0; z < 2; z++) |
|
| 525 |
+ {
|
|
| 526 |
+ Instruction::Flag cFlag = (c ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 527 |
+ Instruction::Flag zFlag = (z ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 528 |
+ |
|
| 529 |
+ instruction = Instruction(0b11111000, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag); |
|
| 530 |
+ |
|
| 531 |
+ if(c & z) |
|
| 532 |
+ {
|
|
| 533 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 534 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 535 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 536 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 537 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 538 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 539 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 540 |
+ } |
|
| 541 |
+ else |
|
| 542 |
+ {
|
|
| 543 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 544 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 545 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 546 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 547 |
+ } |
|
| 548 |
+ |
|
| 549 |
+ this->uRomData.addInstruction(instruction); |
|
| 550 |
+ } |
|
| 551 |
+ } |
|
| 552 |
+ |
|
| 553 |
+ // JNE addr |
|
| 554 |
+ for(int c = 0; c < 2; c++) |
|
| 555 |
+ {
|
|
| 556 |
+ for(int z = 0; z < 2; z++) |
|
| 557 |
+ {
|
|
| 558 |
+ Instruction::Flag cFlag = (c ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 559 |
+ Instruction::Flag zFlag = (z ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 560 |
+ |
|
| 561 |
+ instruction = Instruction(0b11111001, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag); |
|
| 562 |
+ |
|
| 563 |
+ if(!(c & z)) |
|
| 564 |
+ {
|
|
| 565 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 566 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 567 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 568 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 569 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 570 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 571 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 572 |
+ } |
|
| 573 |
+ else |
|
| 574 |
+ {
|
|
| 575 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 576 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 577 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 578 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 579 |
+ } |
|
| 580 |
+ |
|
| 581 |
+ this->uRomData.addInstruction(instruction); |
|
| 582 |
+ } |
|
| 583 |
+ } |
|
| 584 |
+ |
|
| 585 |
+ // JG addr |
|
| 586 |
+ for(int c = 0; c < 2; c++) |
|
| 587 |
+ {
|
|
| 588 |
+ for(int z = 0; z < 2; z++) |
|
| 589 |
+ {
|
|
| 590 |
+ Instruction::Flag cFlag = (c ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 591 |
+ Instruction::Flag zFlag = (z ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 592 |
+ |
|
| 593 |
+ instruction = Instruction(0b11111010, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag); |
|
| 594 |
+ |
|
| 595 |
+ if(c & !z) |
|
| 596 |
+ {
|
|
| 597 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 598 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 599 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 600 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 601 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 602 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 603 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 604 |
+ } |
|
| 605 |
+ else |
|
| 606 |
+ {
|
|
| 607 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 608 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 609 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 610 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 611 |
+ } |
|
| 612 |
+ |
|
| 613 |
+ this->uRomData.addInstruction(instruction); |
|
| 614 |
+ } |
|
| 615 |
+ } |
|
| 616 |
+ |
|
| 617 |
+ // JGE addr |
|
| 618 |
+ for(int c = 0; c < 2; c++) |
|
| 619 |
+ {
|
|
| 620 |
+ for(int z = 0; z < 2; z++) |
|
| 621 |
+ {
|
|
| 622 |
+ Instruction::Flag cFlag = (c ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 623 |
+ Instruction::Flag zFlag = (z ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 624 |
+ |
|
| 625 |
+ instruction = Instruction(0b11111011, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag); |
|
| 626 |
+ |
|
| 627 |
+ if(c) |
|
| 628 |
+ {
|
|
| 629 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 630 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 631 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 632 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 633 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 634 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 635 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 636 |
+ } |
|
| 637 |
+ else |
|
| 638 |
+ {
|
|
| 639 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 640 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 641 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 642 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 643 |
+ } |
|
| 644 |
+ |
|
| 645 |
+ this->uRomData.addInstruction(instruction); |
|
| 646 |
+ } |
|
| 647 |
+ } |
|
| 648 |
+ |
|
| 649 |
+ // JL addr |
|
| 650 |
+ for(int c = 0; c < 2; c++) |
|
| 651 |
+ {
|
|
| 652 |
+ for(int z = 0; z < 2; z++) |
|
| 653 |
+ {
|
|
| 654 |
+ Instruction::Flag cFlag = (c ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 655 |
+ Instruction::Flag zFlag = (z ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 656 |
+ |
|
| 657 |
+ instruction = Instruction(0b11111100, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag); |
|
| 658 |
+ |
|
| 659 |
+ if(!c & !z) |
|
| 660 |
+ {
|
|
| 661 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 662 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 663 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 664 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 665 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 666 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 667 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 668 |
+ } |
|
| 669 |
+ else |
|
| 670 |
+ {
|
|
| 671 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 672 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 673 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 674 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 675 |
+ } |
|
| 676 |
+ |
|
| 677 |
+ this->uRomData.addInstruction(instruction); |
|
| 678 |
+ } |
|
| 679 |
+ } |
|
| 680 |
+ |
|
| 681 |
+ // JLE addr |
|
| 682 |
+ for(int c = 0; c < 2; c++) |
|
| 683 |
+ {
|
|
| 684 |
+ for(int z = 0; z < 2; z++) |
|
| 685 |
+ {
|
|
| 686 |
+ Instruction::Flag cFlag = (c ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 687 |
+ Instruction::Flag zFlag = (z ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 688 |
+ |
|
| 689 |
+ instruction = Instruction(0b11111101, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag); |
|
| 690 |
+ |
|
| 691 |
+ if((!c & !z) || (c & z)) |
|
| 692 |
+ {
|
|
| 693 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 694 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 695 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 696 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 697 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 698 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 699 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 700 |
+ } |
|
| 701 |
+ else |
|
| 702 |
+ {
|
|
| 703 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 704 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 705 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 706 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 707 |
+ } |
|
| 708 |
+ |
|
| 709 |
+ this->uRomData.addInstruction(instruction); |
|
| 710 |
+ } |
|
| 711 |
+ } |
|
| 712 |
+ |
|
| 713 |
+ // LOAD_I + STORE + SP+1 + RPC+1 // ======================================= |
|
| 714 |
+ |
|
| 715 |
+ // PUSH reg |
|
| 716 |
+ instruction = Instruction(0b01100100, Instruction::Arg::ABXY); |
|
| 717 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 718 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::Ram, Step::BusB::Default, Step::BusC::SP)); |
|
| 719 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::SP_PLUS)); |
|
| 720 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 721 |
+ this->uRomData.addInstruction(instruction); |
|
| 722 |
+ |
|
| 723 |
+ // LOAD_I + SP-1 + STORE + RPC+1 // ======================================= |
|
| 724 |
+ |
|
| 725 |
+ // POP reg |
|
| 726 |
+ instruction = Instruction(0b01101000, Instruction::Arg::ABXY); |
|
| 727 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 728 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::SP_MINUS)); |
|
| 729 |
+ instruction.addStep(Step(Step::BusAR::Ram, Step::BusAW::ABXY, Step::BusB::Default, Step::BusC::SP)); |
|
| 730 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 731 |
+ this->uRomData.addInstruction(instruction); |
|
| 732 |
+ |
|
| 733 |
+ // LOAD_I + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + SP+1 + STORE + SP+1 + RESET // |
|
| 734 |
+ |
|
| 735 |
+ // CALL addr |
|
| 736 |
+ instruction = Instruction(0b11110001, Instruction::Arg::Addr); |
|
| 737 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 738 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 739 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 740 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 741 |
+ instruction.addStep(Step(Step::BusAR::PCL, Step::BusAW::Ram, Step::BusB::Default, Step::BusC::SP)); |
|
| 742 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::SP_PLUS)); |
|
| 743 |
+ instruction.addStep(Step(Step::BusAR::PCH, Step::BusAW::Ram, Step::BusB::Default, Step::BusC::SP)); |
|
| 744 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::SP_PLUS)); |
|
| 745 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 746 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 747 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 748 |
+ this->uRomData.addInstruction(instruction); |
|
| 749 |
+ |
|
| 750 |
+ // LOAD_I + SP-1 + STORE + SP-1 + STORE + RPC+1 // ======================== |
|
| 751 |
+ |
|
| 752 |
+ // RET |
|
| 753 |
+ instruction = Instruction(0b11110010); |
|
| 754 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 755 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::SP_MINUS)); |
|
| 756 |
+ instruction.addStep(Step(Step::BusAR::Ram, Step::BusAW::PCH, Step::BusB::Default, Step::BusC::SP)); |
|
| 757 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::SP_MINUS)); |
|
| 758 |
+ instruction.addStep(Step(Step::BusAR::Ram, Step::BusAW::PCL, Step::BusB::Default, Step::BusC::SP)); |
|
| 759 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 760 |
+ this->uRomData.addInstruction(instruction); |
|
| 761 |
+ |
|
| 762 |
+ // LOAD_I + ALU + PC+1 + PC+1 + RPC+1 // ================================== |
|
| 763 |
+ // + ALU + STORE + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + RESET // |
|
| 764 |
+ |
|
| 765 |
+ // LOOPE reg, reg, addr |
|
| 766 |
+ for(int c = 0; c < 2; c++) |
|
| 767 |
+ {
|
|
| 768 |
+ for(int z = 0; z < 2; z++) |
|
| 769 |
+ {
|
|
| 770 |
+ Instruction::Flag cFlag = (c ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 771 |
+ Instruction::Flag zFlag = (z ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 772 |
+ |
|
| 773 |
+ instruction = Instruction(0b11101000, Instruction::Arg::AB, Instruction::Arg::ABXY, Instruction::Arg::Addr, cFlag, zFlag); |
|
| 774 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 775 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::AB, Step::BusC::Default, 0b0110, false, true)); |
|
| 776 |
+ |
|
| 777 |
+ if(c & z) |
|
| 778 |
+ {
|
|
| 779 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 780 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 781 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 782 |
+ } |
|
| 783 |
+ else |
|
| 784 |
+ {
|
|
| 785 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 786 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 787 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 788 |
+ } |
|
| 789 |
+ |
|
| 790 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 791 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 792 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, false)); |
|
| 793 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 794 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 795 |
+ this->uRomData.addInstruction(instruction); |
|
| 796 |
+ } |
|
| 797 |
+ } |
|
| 798 |
+ |
|
| 799 |
+ // LOAD_I + ALU + STORE + PC+1 + PC+1 + PC+1 + RPC+1 // =================== |
|
| 800 |
+ // + ALU + STORE + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + RESET // |
|
| 801 |
+ |
|
| 802 |
+ // LOOPE val, reg, addr |
|
| 803 |
+ for(int c = 0; c < 2; c++) |
|
| 804 |
+ {
|
|
| 805 |
+ for(int z = 0; z < 2; z++) |
|
| 806 |
+ {
|
|
| 807 |
+ Instruction::Flag cFlag = (c ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 808 |
+ Instruction::Flag zFlag = (z ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 809 |
+ |
|
| 810 |
+ instruction = Instruction(0b01001100, Instruction::Arg::Val256, Instruction::Arg::ABXY, Instruction::Arg::Addr, cFlag, zFlag); |
|
| 811 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 812 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 813 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 814 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b0110, false, true)); |
|
| 815 |
+ |
|
| 816 |
+ if(c & z) |
|
| 817 |
+ {
|
|
| 818 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 819 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 820 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 821 |
+ } |
|
| 822 |
+ else |
|
| 823 |
+ {
|
|
| 824 |
+ |
|
| 825 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 826 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 827 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 828 |
+ } |
|
| 829 |
+ |
|
| 830 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 831 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 832 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0000, false, false)); |
|
| 833 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 834 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 835 |
+ this->uRomData.addInstruction(instruction); |
|
| 836 |
+ } |
|
| 837 |
+ } |
|
| 838 |
+ |
|
| 839 |
+ // LOAD_I + ALU STORE + PC+1 + PC+1 + RPC+1 // ============================ |
|
| 840 |
+ // + ALU + STORE + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + RESET // |
|
| 841 |
+ |
|
| 842 |
+ // LOOPZ reg, addr |
|
| 843 |
+ for(int c = 0; c < 2; c++) |
|
| 844 |
+ {
|
|
| 845 |
+ for(int z = 0; z < 2; z++) |
|
| 846 |
+ {
|
|
| 847 |
+ Instruction::Flag cFlag = (c ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 848 |
+ Instruction::Flag zFlag = (z ? Instruction::Flag::Enable : Instruction::Flag::Disable); |
|
| 849 |
+ |
|
| 850 |
+ instruction = Instruction(0b11110100, Instruction::Arg::ABXY, Instruction::Arg::Addr, Instruction::Arg::None, cFlag, zFlag); |
|
| 851 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::I)); |
|
| 852 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b0011, false, false)); |
|
| 853 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::D)); |
|
| 854 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b0110, false, true)); |
|
| 855 |
+ |
|
| 856 |
+ if(c & z) |
|
| 857 |
+ {
|
|
| 858 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 859 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 860 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC_PLUS)); |
|
| 861 |
+ } |
|
| 862 |
+ else |
|
| 863 |
+ {
|
|
| 864 |
+ |
|
| 865 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 866 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::D)); |
|
| 867 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::PC_PLUS)); |
|
| 868 |
+ } |
|
| 869 |
+ |
|
| 870 |
+ instruction.addStep(Step(Step::BusAR::Flash, Step::BusAW::PCH)); |
|
| 871 |
+ instruction.addStep(Step(Step::BusAR::D, Step::BusAW::PCL)); |
|
| 872 |
+ instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::Default, Step::BusC::Default, 0b1111, false, true)); |
|
| 873 |
+ instruction.addStep(Step(Step::BusAR::T, Step::BusAW::ABXY)); |
|
| 874 |
+ instruction.addStep(Step(Step::BusAR::Default, Step::BusAW::RPC)); |
|
| 875 |
+ |
|
| 876 |
+ this->uRomData.addInstruction(instruction); |
|
| 877 |
+ } |
|
| 878 |
+ } |
|
| 879 |
+} |
|
| 880 |
+ |
|
| 881 |
+/** |
|
| 882 |
+ * Save a binary microcode to files |
|
| 883 |
+ * |
|
| 884 |
+ * @param urom0Path Path to the first output file |
|
| 885 |
+ * @param urom1Path Path to the second output file |
|
| 886 |
+ * |
|
| 887 |
+ * @return Status of the save operation |
|
| 888 |
+ */ |
|
| 889 |
+bool URom::saveFiles(const QString &urom0Path, const QString &urom1Path) |
|
| 890 |
+{
|
|
| 891 |
+ // Try to save the data to the output files |
|
| 892 |
+ return(this->uRomData.saveFiles(urom0Path, urom1Path)); |
|
| 893 |
+} |